As scaling conventional planar complementary metal-oxide semiconductor (CMOS) becomes increasingly challenging, several non-planar device structures have been considered. One such non-planar device structure is a gate all around field effect transistor (FET). A gate all around FET achieves superior short channel characteristics from the electrostatics that the geometry of the structure provides. In fact, in some situations there is actually overscaling (i.e., better electrostatics than required).
However, one issue with gate all around FETs is in maintaining effective device width scaling after the various nanowire formation processes. One solution to this problem is to create stacked layered structures. To create layered structures, however, creates additional process complexities. Another solution is to pattern large nanowires which, as patterned, have a small spacing between the nanowires. Such a patterning process, however, is very difficult to control and to produce a reliable yield.
Therefore, techniques for maintaining desired device width in process flows that involve nanowire thinning would be desirable.